3.3 V) from the carrier to the mezzanine card (max.
It is used to power the IO Bank of the FPGA.ģ.3 V auxiliary power supply (max. This voltage is sourced by the mezzanine module which supports the HB bus. Reference voltage for signaling standard of bank B (HBxx).
Reference voltage for signaling standard of bank A (LAxx and HAxx). These pins are driven by the carrier card. Geographical address of the module (can be used for adressing on I2C bus). Multi-gigabit transceiver data pairs (one is mandatory for LPC, 10 in total with HPC) Connection is made on the mezzanine module.Ĭlock signals for multi-gigabit transceiver data pairs (GBTCLK1_x only for HPC) 3P3V via 10k pull-up resistor if the carrier card drives the clock signals. GND (or floating) if the mezzanine module is the driver. These pins can be used for clock signals.Ģ user clocks, differential pairs, driver is the mezzanine moduleĢ user clocks, differential pairs, bidirectional (driver is determined by CLK_DIR pin)ĭetermines the driver for CLK_BIDIR. HB_XX - HPC, FPGA Bank B,44 user-defined, single-ended signals or 22 user-defined, differential pairs HA_XX - HPC, FPGA Bank A,48 user-defined, single-ended signals or 24 user-defined, differential pairs LA_XX - LPC, FPGA Bank A,68 user-defined, single-ended signals or 34 user-defined, differential pairs (mandatory for LPC)
The following table summarizes the pins of the LPC connector. The LPC connector has 4 rows (C, D, G, H) with 40 pins each. Low-pin count (LPC) connector, LPC pinout HPC connector pin summaryįootprints can be viewed in Lib_Altium repository. The following table summarizes the pins of the HPC connector.
The HPC connector has 10 rows (A, B, C, D, E, F, G, H, J, K) with 40 pins each. High-pin count (HPC) connector, HPC pinout Generated by FMCHUB - FPGA MEZZANINE CARDs High-pin count (HPC) connector, HPC pinoutĢ. VITA 57 FPGA Mezzanine Card (FMC) SIGNALS AND PINOUT OF HIGH-PIN COUNT (HPC) AND LOW-PIN COUNT (LPC) CONNECTORSġ.
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